The invention relates to a semiconductor device, and more particularly to a high frequency and high speed field effect transistor with an improved Schottky gate structure.
Improvements and developments of high frequency and high speed field effect transistors made of compound semiconductors such as InP, InGaAs or other compound semiconductors including In are very important for revolutions in semiconductor field. Compound semiconductors such as InP, InGaAs and other compound semiconductors including In are suitable for high frequency and high speed fiend effect transistors as having a property of a high electron mobility. Such high electron mobility field effect transistor showing high frequency and high speed performances have a Schottky gate contact. Namely, a gate electrode made of a metal has to be provided directly on a semiconductor layer so that the gate electrode is electrically separated from the semiconductor layers through the Schottky barrier. As well known, a semiconductor-metal contact or Schottky contact provides a conduction band discontinuity which serves as a potential barrier or Schottky barrier which prevents electrons acting as carriers to flow across the Schottky contact from the metal toward the semiconductor. A sufficient height of the Schottky barrier is necessary to suppress a gate leakage current or to suppress electrons to flow across the Schottky contact from the metal toward the semiconductor.
Using InP or InGaAs for high frequency and high speed transistors is disclosed in U.K. Mishra 1989 IEEE Transaction on Microwave Theory and Techniques, Vol. 37, No. 9 p. 1279. The structure of the deice is as follows. A substrate is a semi-insulating InP substrate. A buffer layer made of InAlAs is formed on the semi-insulating InP substrate. A non-doped InGaAs layer is formed on the InAlAs buffer layer. An n-type InAlAs layer is formed on the non-doped InGaAs layer to form a hereto junction therewith. A non-doped InAlAs layer is formed on the n-type InAlAs layer. The above layers may sequentially be grown on the substrate. A gate electrode is provided on the non-doped InAlAs layer to form a Schottky contact therewith.
The non-doped InAlAs layer is provided to form a Schottky barrier in cooperation with the gate electrode. Such the Schottky barrier serve to prevent electrons acting as carriers to flow across the Schottky contact surface. Although the non-doped InAlAs layer is provided to suppress a gate leakage current, a Schottky barrier height is 0.55 eV which seems insufficient to suppress a gate leakage current in view of a voltage applied to the gate electrode. Much more high Schottky barrier is required to realize a sufficient suppression of the gate leakage current or to suppress electrons acting as carriers to move across the Schottky contact surface from the metal region of the gate electrode into the semiconductor region.
Another high electron mobility transistor is disclosed in May 1993 IEEE Electron Device Letters, Vol. 14, No. 5 pp.-259-261. The structure of the transistor is as follows. A semiconductor substrate is a semi-insulating InP substrate. An undoped InP layer having a thickness of 10 nanometers is formed on the semi-insulating InP substrate. An undoped InGaAs layer having a thickness of 20 nanometers is formed on the undoped InP layer. An undoped InAlAs layer having a thickness of 3 nanometers is formed on the undoped InGaAs layer. An n.sup.+ -doped InAlAs layer having a thickness of 15 nanometers and an impurity concentration of 3.times.10.sup.18 cm.sup.-3 is formed on the undoped InAlAs layer. An undoped In.sub.0.75 Ga.sub.0.25 P layer having a thickness of 10 nanometers is formed on the n.sup.+ -doped InAlAs layer. A recess etched cap layer made of n.sup.+ -doped InGaAs having a thickness of 20 nanometers and an impurity concentration of 5.times.10.sup.18 cm.sup.-3 is formed on the undoped In.sub.0.75 Ga.sub.0.25 P layer. Source and drain electrodes are provided on the cap layer. A gate electrode is provided on an exposed surface of the undoped In.sub.0.75 Ga.sub.0.25 P layer in a recess portion. This transistor is so designed as to allow high frequency and high speed performances, while a Schottky barrier height is insufficient for a potential barrier to suppress a gate leakage current or prevent electrons acting as carriers to flow across the Schottky interface from the gate into the In.sub.0.75 Ga.sub.0.25 P layer. Much more high Schottky barrier is also needed.
To combat the above problems as to the gate leakage current, another Schottky gate structures were proposed and disclosed in the Japanese laid-open patent applications Nos. 64-41272 and 64-41273. The Japanese laid-open patent application No. 64-41272 describes inserting a superlattice structure of AlGaAs/AlInAs under the gate electrode in which the superlattice structure may serve as a potential barrier to suppress a gate leakage current or prevent electrons acting as carriers to flow across the Schottky contact surface into an Al.sub.0.48 In.sub.0.52 As layer. The Japanese laid-open patent application No. 64-41273 also describes inserting an Al.sub.0.4 Ga.sub.0.6 As layer under the gate electrode in which the superlattice structure may serve as a potential barrier to suppress a gate leakage current or prevent electrons acting as carriers to flow across the Schottky contact surface into an Al.sub.0.48 In.sub.0.52 As layer. The Al.sub.0.4 Ga.sub.0.6 As layer is required to have a thickness less than a critical thickness of approximately 10 nanometers in view of lattice matching. The superlattice structure of AlGaAs/AlInAs is also required to have the sum of individual thicknesses of AlGaAs layers less than a critical thickness which is very thin.
Typical structure of the above field effect transistors are illustrated in FIG. 1. The field effect transistor has an InP semi-insulating substrate 101. A layer 102 made of compound semiconductors including In is formed on the InP semi-insulating substrate 101. An InAlAs layer 103 is formed on the layer 102. An AlGaAs layer 104 is formed on the InAlAs layer 103. Recess etched n-doped InGaAs cap layers 107-1 and 107-2 serving as source and drain regions are formed on the AlGaAs layer 104. Source and drain electrodes 108-1 and 108-2 are provided on the source and drain regions 107-1 and 107-2. A gate electrode 109 is provided in a recess portion. The AlGaAs layer constitutes a potential barrier against electrons serving as carriers to prevent electrons flow across a Schottky contact from the gate electrode 109 into the InAlAs layer 103 so as to suppress a Schottky gate leakage current.
Such Schottky barrier structures are engaged with the following problems in fabricating the device. Recess etching of the cap layer serving as source and drain regions is necessary to form such a Schottky barrier gate. Although the recess etching is continued until the barrier layer is exposed, it is difficult to control the recess etching to discontinue the recess etching just when a surface of the barrier layer is exposed in view of etching accuracy. Actually, the AlGaAs layer serving as a potential barrier seems to suffer damage from the recess etching process to form a recess portion in which the Schottky gate electrode is provided. The potential barrier layer, once damaged due to the recess etching process, is no longer able to serve a potential barrier for suppressing a gate leakage current. This is the serious problem. The above superlattice structure serving as a potential barrier is also engaged with the same problem as described above. It would be required to develop a potential barrier structure in which the potential barrier layer is free from any damage due to the recess etching.
Another high electron mobility transistor having a potential barrier structure against holes acting as positive carriers in which a potential barrier layer is provided adjacent to a channel layer is disclosed in Inst. Phys. Conf. Ser. No 129 Chapter 12, pp. 941-942. The structure of high electron mobility transistor is as follows. A semiconductor substrate is a InP substrate. A buffer layer is formed on the semiconductor substrate. An InGaAs channel layer having a thickness of 40 nanometers is formed on the buffer layer. An n-doped InAlAs spacer layer having a thickness of 1.5 nanometers is is formed on the InGaAs channel layer. An InAlAs hole barrier layer having a thickness of 3 nanometers is formed on the n-doped InAlAs spacer layer. An n-doped InAlAs spacer Layer having a thickness of 1.5 nanometers is formed on the InAlAs hole barrier layer. An n.sup.+ -doped InAlAs layer having a thickness of 11 nanometers is formed on the n-doped InAlAs spacer layer. An n-doped InAlAs layer having a thickness of 20 nanometers is formed on the n.sup.' -doped InAlAs layer. A recess etched cap layer made of InGaAs is formed on the n-doped InAlAs layer. Source and drain electrodes are provided on the cap layer. A gate electrode is provided on an exposure surface of the n-doped InAlAs in the recess portion to form a Schottky contact structure.
The InAlAs hole barrier layer is also able to serve as a potential barrier but against holes acting as carriers. The hole barrier layer serves merely as a potential barrier to hole carriers so as to prevent the hole carriers to flow out from the channel layer. For that purpose, it is required to provide the hole barrier layer adjacent to the channel layer. However, such the hole barrier layer would never be a potential barrier against electrons. Actually, it could readily be appreciated that the hole barrier adjacent to the channel layer is unable to suppress electrons to flow across the Schottky barrier from the Schottky gate electrode into the semiconductor layers. Although the electron barrier and the hole barrier fill the same role merely in view of suppressing a gate leakage current, the both barriers are on the bases of the completely different principles. Suppressing electron carriers to flow across the Schottky barrier contact surface from the Schottky gate into the semiconductor layer would completely be different technical viewpoint from suppressing hole carriers to flow out from the channel layer. In the former case the electron barrier is required to be provided adjacent to the Schottky gate contact, while in the latter case the hole barrier is required to be provided adjacent to the channel layer.
The prior art discussed above neither describes nor teaches an ideal Schottky barrier structure to suppress electrons to flow across a Schottky contact surface from a Schottky gate electrode into a semiconductor layer in which a Schottky barrier layer provided adjacent to the Schottky contact is free from any damage due to a recess etching process.
It would, therefore, be required to develop a novel Scottky gate structure with an improved electron barrier involved in a high frequency and high speed field effect transistor of compound semiconductors.